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general description the max8513/max8514 integrate a voltage-mode pwm step-down dc-dc controller and two ldo con- trollers, a voltage monitor, and a power-on reset for the lowest-cost power-supply and monitoring solution for xdsl modems, routers, gateways, and set-top boxes. the dc-dc controller switching frequency can be set with an external resistor from 300khz to 1.4mhz, to allow for the optimization of cost, size, and efficiency. for noise- sensitive applications, the dc-dc controller can also be synchronized to an external clock, minimizing noise inter- ference. operation above 1.1mhz reduces noise for high data-rate xdsl applications. an adjustable soft-start and adjustable foldback current limit provide reliable startup and fault protection. the dc-dc controller output voltage can be set externally to a voltage from 1.25v to 5.5v. current limiting is accomplished by inductor current sens- ing for improved efficiency, or by an external sense resis- tor for better accuracy. the max8513/max8514s?first ldo controller is designed to provide a low-cost, high-current regulated output from 0.8v to 5.5v using an n-channel mosfet or a low-current output using a low-cost npn transistor. the max8513? second regulator can be used to generate 0.8v to 27v output with a low-cost pnp transistor. both ldo regulators can operate either from the dc-dc con- troller output or from a higher voltage derived with a fly- back overwinding on the dc-dc converter inductor. the max8514? second ldo regulator is designed to pro- vide a negative output with an npn transistor. a sequence input allows the outputs to either power up together, or for the dc-dc regulator to power up first and each ldo controller to power up in sequence. an input power-fail output ( pfo ) is provided for input power-fail warning, such as in dying-gasp applications. a power-on reset circuit with a 140ms delay is also included to indicate when all outputs have achieved regulation and stabilized. applications xdsl, cable, isdn modems, and routers wireless routers set-top boxes automotive dashboard electronics features ? low-cost dc-dc controller with two ldos ? wide input range: 4.5v to 28v ? 300khz to 1.4mhz adjustable switching frequency ? low noise for high data-rate xdsl applications ? synchronizable to external clock ? adjustable soft-start ? lossless adjustable foldback current limit ? power-on reset with 140ms delay ? adjustable input power-fail warning for dying gasp ? selectable output-voltage sequencing or output-voltage tracking max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset ________________________________________________________________ maxim integrated products 1 step- down controller v in (4.5v to 28v) v out1 (1.25v to 5.5v) v out2 (0.8v to v out1 ) v out3 (0.8v to 27v) ldo controller 1 ldo controller 2 output power-on reset input power- f ail monitor max8513 sync on off functional diagram ordering information 19-3178; rev 0; 2/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package max8513 eei -40 c to +85 c 28 qsop max8514 eei -40 c to +85 c 28 qsop MAX8514AEI -40 c to +125 c 28 qsop pin configurations appear at end of data sheet.
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v in = v lx = v sup2 = 12v, v pvl = v bst - v lx = v drv3p = 5v, v sup3n = 3.3v, v drv3n = -5v, c vl = 4.7?, c ref = 0.22?, r freq = 15.0k ? , t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in, drv3p, sup2 to gnd.......................................-0.3v to +30v drv2 to gnd ..........................................-0.3v to (v sup2 + 0.3v) drv3n to gnd......................(v sup3n - 28v) to (v sup3n + 0.3v) freq, pfi, pfo , por , sup3n, sync/en, csp, csn to gnd ................................................-0.3v to +6v vl to gnd ...................-0.3v to the lesser of (v in + 0.3v) or +6v comp1, fb1, fb2, fb3p, fb3n, ref, ilim, ss, seq to gnd......................................-0.3v to (v vl + 0.3v) pvl to pgnd ............................................................-0.3v to +6v dl to pgnd...............................................-0.3v to (v pvl + 0.3v) bst to lx..................................................................-0.3v to +6v dh to lx ....................................................-0.3v to (v bst + 0.3v) pgnd to gnd .......................................................-0.3v to +0.3v vl short circuit to gnd .............................................continuous continuous power dissipation (t a = +70?) 28-pin qsop (derate 10.8mw/ c above +70 c).........860mw operating temperature range max8513eei, max8514eei .............................-40 c to +85 c MAX8514AEI..................................................-40 c to +125 c junction temperature ......................................................+150 c storage temperature range .............................-65 c to +150 c lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units general 5.5 28.0 in operating range in = vl 4.5 5.5 v in supply current v fb1 = 1.3v, v fb2 = v fb3 = 1.0v, does not include switching current to pvl and bst, sync/en = vl 2.6 3.2 ma in shutdown current v sync/en = 0, r freq = 50k ? 200 300 ? vl regulator vl output voltage v in = 6v to 28v, i vl = 0.1ma to 40ma 4.75 5 5.25 v vl dropout voltage from in to vl, v in = 5v, i vl = 40ma 560 mv vl line regulation v in = 6v to 28v, i vl = 5ma 0.05 % vl undervoltage threshold vl rising, v hyst = 675mv (typ) 3.6 4.2 v out1 (buck converter) output voltage range v out1 (note 1) 1.25 5.50 v fb1 regulation threshold v fb1 1.234 1.25 1.259 v error-amplifier open-loop voltage gain a vol 65 90 db fb1 input bias current i fb1_bias v fb1 = 1.3v -200 +10 +200 na error-amplifier gain bandwidth 25 mhz dh output-resistance high r dh_high 1.5 2.55 ? dh output-resistance low r dh_low 1.2 2.1 ? dl output-resistance high r dl_high 2.5 5 ? dl output-resistance low r dl_low 0.7 1.3 ? driver dead time t dt starts from v dl = 1v or (v dh - v lx ) = 1v 50 ns
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset _______________________________________________________________________________________ 3 electrical characteristics (continued) (v in = v lx = v sup2 = 12v, v pvl = v bst - v lx = v drv3p = 5v, v sup3n = 3.3v, v drv3n = -5v, c vl = 4.7?, c ref = 0.22?, r freq = 15.0k ? , t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units v ilim = 2.00v, v csn = 0 to 5.5v 246 275 300 v ilim = 0.50v, v csn = 0 to 5.5v 50 67 81 current-limit threshold (positive) v cs v ilim = v vl , v csn = 0 to 5.5v 151 170 188 mv v ilim = 2.00v, v csn = 0 to 5.5v -333 -272 -199 v ilim = 0.50v, v csn = 0 to 5.5v -90 -67 -42 current-limit threshold (negative) v cs v ilim = v vl , v csn = 0 to 5.5v -210 -166 -122 mv csp and csn bias current v csp = v csn = 0 to 5.5v -120 +135 ? ilim bias current v ilim = 1.25v -5.3 -5 -4.7 ? ss soft-start charge current v ss = 0.6v 15 25 35 ? soft-start discharge resistance 100 200 ? lx, bst, pvl leakage current v lx = v in = 28v, v bst = 33v, v pvl = 5v, v sync/en = 0 0.03 20 ? fb1 power-on reset threshold 1.08 1.125 1.20 v out2 (positive ldo) sup2 operating range v sup2 (note 1) 4.5 28.0 v drv2 clamp voltage v drv2 v fb2 = 0.75v 7.75 9.00 v sup2 supply current 160 300 ? sup2 shutdown supply current v sync/en = 0 3 10 ? fb2 regulation voltage v fb2 0.784 0.80 0.808 v fb2 input bias current i fb2_bias v fb2 = 0.75v 0.01 100 na drv2 output current limit v in = 5v, v drv2 = 5v, v fb2 = 0.77v 15 30 ma drv2 output current limit during soft-start v in = 6v, v drv2 = 5v, v fb2 = 0.70v 8 10 12 ma fb2 power-on reset threshold 0.690 0.720 0.742 v fb2 to drv2 transconductance g c2 i drv2 = +250?, -250? 0.12 0.2 0.36 s out3p (positive pnp ldo) (max8513 only) drv3p operating range v drv3p 128v fb3p regulation voltage v drv3p = 5v, i drv3p = 1ma 0.790 0.803 0.816 v fb3p to drv3p large-signal transconductance g c3p v drv3p = 5v, i drv3p = 0.5ma to 5ma 0.38 0.6 1.1 s feedback input bias current v fb3p = 0.75v 0.01 100 na drv3p = 2.5v 15 35 driver sink current v fb3p = 0.75v drv3p = 4.0v 40 ma fb3p por threshold 0.690 0.720 0.742 v fb3p soft-start period 1312 clock cycles
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset 4 _______________________________________________________________________________________ electrical characteristics (continued) (v in = v lx = v sup2 = 12v, v pvl = v bst - v lx = v drv3p = 5v, v sup3n = 3.3v, v drv3n = -5v, c vl = 4.7?, c ref = 0.22?, r freq = 15.0k ? , t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units out3n (negative npn ldo controller) (max8514 only) sup3n operating range (note 1) 1.5 5.5 v drv3n operating range (note 1) v sup3n - 21v v sup3n - 1.5v v sup3n supply current v drv3n = 1.5v, v sup3n = 3.5v, i drv3n = -1ma (source) 1.1 2 ma fb3n regulation voltage v drv3n = 1.5v, v sup3n = 3.5v, i drv3n = -1ma (source) -20 -5 +10 mv fb3n to drv3n large-signal transconductance g c3n v drv3n = 0, i drv3n = -0.5ma to -5ma (source) 0.225 0.36 0.550 s feedback input bias current v fb3n = -100mv 60 1000 na driver source current v fb3n = 200mv, v drv3n = 0, v sup3n = 3.5v 13 25 ma fb3n por threshold 450 500 550 mv fb3n soft-start period 2048 clock cycles reference ref output voltage v ref -2? < i ref < +50? 1.231 1.25 1.269 v oscillator r freq = 10.7k ? ?% from freq to gnd 1300 1390 1460 r freq = 15.0k ? ?% from freq to gnd 933 985 1040 frequency f s r freq = 50.0k ? ?% from freq to gnd 260 290 324 khz freq resistance-frequency product 15.0 mhz k ? r freq = 10.7k ? ?% from freq to gnd 77 83 91 r freq = 15.0k ? ?% from freq to gnd 80 87 95 maximum duty cycle (measured at dh pin) r freq = 50.0k ? ?% from freq to gnd 93 96 99 % minimum on-time (measured at dh pin) r freq = 10.7k ? ?% from freq to gnd 20 62 ns sync/en pulse width low or high (note 1) 200 ns sync/en frequency range sync/en input frequency needs to be within ?0% of the value set at the freq pin (note 1) 200 1850 khz sync/en input voltage, high 2.4 v sync/en input voltage, low 0.8 v sync/en input current v sync/en = 0 to 5.5v -1 +1 ?
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset _______________________________________________________________________________________ 5 electrical characteristics (continued) (v in = v lx = v sup2 = 12v, v pvl = v bst - v lx = v drv3p = 5v, v sup3n = 3.3v, v drv3n = -5v, c vl = 4.7?, c ref = 0.22?, r freq = 15.0k ? , t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) electrical characteristics (v in = v lx = v sup2 = 12v, v pvl = v bst - v lx = v drv3p = 5v, v sup3n = 3.3v, v drv3n = -5v, c vl = 4.7?, c ref = 0.22?, r freq = 15.0k ? , t a = -40? to +125? (note 2), unless otherwise noted.) parameter symbol conditions min typ max units seq, pfi, pfo , por seq input-voltage high 2.4 v seq input-voltage low 0.8 v seq input current v seq = 0 to v vl 110a i por = 1.6ma 10 200 por output-voltage low v fb1 , v fb2 , v fb3p , v fb3n , out-of-regulation i por = 0.1ma, v in = 1.0v 20 200 mv por output leakage current v fb1 , v fb2 , and v fb3p or v fb3n , in- regulation 0.001 1 a por power-ready delay time from v fb1 , v fb2 , and v fb3p or v fb3n , in- regulation to por = high impedance 140 315 560 ms pfi input threshold falling, v hyst = 20mv 1.20 1.22 1.25 v pfi input bias current v pfi = 1.0v 0.1 100 na i pfo = 1.6ma 20 200 pfo output-voltage low pfi = 1.1v i pfo = 0.1ma, v in = 1.0v 10 200 mv pfo output leakage current pfi = 1.4v, pfo = 5v 0.001 1 a thermal protection thermal shutdown junction temperature rising +170 ? thermal-shutdown hysteresis 25 ? parameter symbol conditions min max units general 5.5 28.0 in operating range in = vl 4.5 5.5 v in supply current v fb1 = 1.3v, v fb2 = v fb3 = 1.0v, does not include switching current to pvl and bst, sync/en = vl 3.2 ma in shutdown current v sync/en = 0, r freq = 50k ? 300 ? vl regulator vl output voltage v in = 6v to 28v, i vl = 0.1ma to 40ma 4.75 5.25 v vl dropout voltage from in to vl, v in = 5v, i vl = 40ma 610 mv vl undervoltage threshold vl rising, v hyst = 675mv (typ) 3.6 4.2 v
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset 6 _______________________________________________________________________________________ electrical characteristics (continued) (v in = v lx = v sup2 = 12v, v pvl = v bst - v lx = v drv3p = 5v, v sup3n = 3.3v, v drv3n = -5v, c vl = 4.7?, c ref = 0.22?, r freq = 15.0k ? , t a = -40? to +125? (note 2), unless otherwise noted.) parameter symbol conditions min max units out1 (buck converter) output voltage range v out1 (note 1) 1.25 5.50 v fb1 regulation threshold v fb1 1.225 1.265 v error-amplifier open-loop voltage gain a vol 65 db fb1 input bias current i fb1_bias v fb1 = 1.3v -200 +200 na dh output-resistance high r dh_high 2.55 ? dh output-resistance low r dh_low 2.1 ? dl output-resistance high r dl_high 5 ? dl output-resistance low r dl_low 1.3 ? v ilim = 2.00v, v csn = 0 to 5.5v 243 303 v ilim = 0.50v, v csn = 0 to 5.5v 49 83 current-limit threshold (positive) v cs v ilim = v vl , v csn = 0 to 5.5v 147 190 mv v ilim = 2.00v, v csn = 0 to 5.5v -333 -199 v ilim = 0.50v, v csn = 0 to 5.5v -90 -42 current-limit threshold (negative) v cs v ilim = v vl , v csn = 0 to 5.5v -210 -122 mv csp and csn bias current v csp = v csn = 0 to 5.5v -120 +135 ? ilim bias current v ilim = 1.25v -5.7 -4.3 ? ss soft-start charge current v ss = 0.6v 15 35 ? soft-start discharge resistance 200 ? lx, bst, pvl leakage current v lx = v in = 28v, v bst = 33v, v pvl = 5v, v sync/en = 0 20 ? fb1 power-on reset threshold 1.08 1.20 v out2 (positive ldo) sup2 operating range v sup2 (note 1) 4.5 28.0 v drv2 clamp voltage v drv2 v fb2 = 0.75v 7.75 9.00 v sup2 supply current 300 ? sup2 shutdown supply current v sync/en = 0 10 a fb2 regulation voltage v fb2 0.775 0.816 v fb2 input bias current i fb2_bias v fb2 = 0.75v 150 na drv2 output current limit v in = 5v, v drv2 = 5v, v fb2 = 0.77v 12 ma drv2 output current limit during soft-start v in = 6v, v drv2 = 5v, v fb2 = 0.70v 8 12 ma fb2 power-on reset threshold 0.690 0.742 v fb2 to drv2 transconductance g c2 i drv2 = +250?, -250? 0.11 0.41 s
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset _______________________________________________________________________________________ 7 electrical characteristics (continued) (v in = v lx = v sup2 = 12v, v pvl = v bst - v lx = v drv3p = 5v, v sup3n = 3.3v, v drv3n = -5v, c vl = 4.7?, c ref = 0.22?, r freq = 15.0k ? , t a = -40? to +125? (note 2), unless otherwise noted.) parameter symbol conditions min max units out3p (positive pnp ldo) (max8513 only) drv3p operating range v drv3p 128v fb3p regulation voltage v drv3p = 5v, i drv3p = 1ma 0.780 0.820 v fb3p to drv3p large-signal transconductance g c3p v drv3p = 5v, i drv3p = 0.5ma to 5ma 0.3 1.4 s feedback input bias current v fb3p = 0.75v 100 na driver sink current v fb3p = 0.75v drv3p = 2.5v 15 ma fb3p por threshold 0.690 0.742 v out3n (negative npn ldo controller) (max8514 only) sup3n operating range (note 1) 1.5 5.5 v drv3n operating range (note 1) v sup3n - 21v v sup3n - 1.5v v sup3n supply current v drv3n = 1.5v, v sup3n = 3.5v, i drv3n = -1ma (source) 2ma fb3n regulation voltage v drv3n = 1.5v, v sup3n = 3.5v, i drv3n = -1ma (source) -20 +10 mv fb3n to drv3n large-signal transconductance g c3n v drv3n = 0, i drv3n = -0.5ma to -5ma (source) 0.225 0.550 s feedback input bias current v fb3n = -100mv 1500 na driver source current v fb3n = 200mv, v drv3n = 0, v sup3n = 3.5v 13 ma fb3n por threshold 450 550 mv reference ref output voltage v ref -2? < i ref < +50? 1.22 1.27 v oscillator r freq = 10.7k ? ?% from freq to gnd 1300 1500 r freq = 15.0k ? ?% from freq to gnd 917 1070 frequency f s r freq = 50.0k ? ?% from freq to gnd 250 335 khz r freq = 10.7k ? ?% from freq to gnd 77 91 r freq = 15.0k ? ?% from freq to gnd 80 95 maximum duty cycle (measured at dh pin) r freq = 50.0k ? ?% from freq to gnd 93 99 % minimum on-time (measured at dh pin) r freq = 10.7k ? ?% from freq to gnd 62 ns sync/en pulse width low or high (note 1) 200 ns sync/en frequency range sync/en input frequency needs to be within ?0% of the value set at the freq pin (note 1) 200 1850 khz
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset 8 _______________________________________________________________________________________ electrical characteristics (continued) (v in = v lx = v sup2 = 12v, v pvl = v bst - v lx = v drv3p = 5v, v sup3n = 3.3v, v drv3n = -5v, c vl = 4.7?, c ref = 0.22?, r freq = 15.0k ? , t a = -40? to +125? (note 2), unless otherwise noted.) parameter symbol conditions min max units sync/en input-voltage high 2.4 v sync/en input-voltage low 0.8 v sync/en input current v sync/en = 0 to 5.5v -1 +1 ? seq, pfi, pfo , por seq input-voltage high 2.4 v seq input-voltage low 0.8 v seq input current v seq = 0 to v vl 10 ? i por = 1.6ma 200 por output-voltage low v fb1 , v fb2 , v fb3p , v fb3n out-of-regulation i por = 0.1ma, v in = 1.0v 200 mv por output leakage current v fb1 , v fb2 , and v fb3p or v fb3n , in- regulation 1a por power-ready delay time from v fb1 , v fb2 , and v fb3p or v fb3n , in- regulation to por = high impedance 140 560 ms pfi input threshold falling, v hyst = 20mv 1.20 1.25 v pfi input bias current v pfi = 1.0v 300 na i pfo = 1.6ma 200 pfo output-voltage low pfi = 1.1v i pfo = 0.1ma, v in = 1.0v 200 mv pfo output leakage current pfi = 1.4v, pfo = 5v 1 a note 1: guaranteed by design, not production tested. note 2: specifications to -40? are guaranteed by design, not production tested.
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset _______________________________________________________________________________________ 9 v out2 vs. i out2 max8513/14 toc04 i out2 (a) v out2 (v) 1.4 1.2 0.8 1.0 0.4 0.6 0.2 2.46 2.47 2.48 2.49 2.50 2.51 2.52 2.53 2.54 2.55 2.45 0 v out1 = 3.3v at 1a v out3 = 12v at 25ma v out3 vs. i out3 max8513/14 toc05 i out3 (ma) v out3 (v) 45 40 30 35 10 15 20 25 5 11.80 11.85 11.90 11.95 12.00 12.05 12.10 12.15 12.20 12.25 11.75 050 v out1 = 3.3v at 1a v out2 = 2.5v at 0.75a v out1 vs. v in max8513/14 toc06 v in (v) v out1 (v) 17 16 14 15 9 10 11 12 13 8 3.26 3.27 3.28 3.29 3.30 3.31 3.32 3.33 3.34 3.35 3.25 718 i out1 = 0 i out1 = 3a v out2 = 2.5v at 0.75a v out3 = 12v at 25ma v out2 vs. v in max8513/14 toc07 v in (v) v out2 (v) 17 16 14 15 9 10 11 12 13 8 2.46 2.47 2.48 2.49 2.50 2.51 2.52 2.53 2.54 2.55 2.45 718 i out2 = 0 i out2 = 1.5a v out1 = 3.3v at 1a v out3 = 12v at 25ma v out3 vs. v in max8513/14 toc08 v in (v) v out3 (v) 17 16 14 15 9 10 11 12 13 8 11.90 11.95 12.00 12.05 12.10 12.15 12.20 12.25 12.30 12.35 11.85 718 i out3 = 0 i out3 = 50ma v out1 = 3.3v at 1a v out2 = 2.5v at 0.75a oscillator frequency vs. input voltage max8513/14 toc09 v in (v) oscillator frequency (mhz) 17 16 14 15 9 10 11 12 13 8 1.37 1.36 1.38 1.39 1.40 1.41 1.42 1.43 1.35 718 r freq = 10.7k ? t a = -40 c t a = +85 c t a = +25 c efficiency vs. input voltage max8513/14 toc01 v in (v) efficiency (%) 17 16 14 15 9 10 11 12 13 8 10 20 30 40 50 60 70 80 90 100 0 718 v out1 = 3.3v, i out1 = 2a v out2 = 2.5v, i out2 = 1.5a v out3 = 12v, i out3 = 50ma efficiency vs. i out1 (i out2 = 0, i out3 = 0) max8513/14 toc02 i out1 (a) efficiency (%) 3.6 4.1 3.1 2.1 2.6 1.1 1.6 0.6 10 20 30 40 50 60 70 80 90 100 0 0.1 v in = 9v v in = 12v v in = 16v v out1 vs. i out1 max8513/14 toc03 i out1 (a) v out1 (v) 3.5 4.0 3.0 2.0 2.5 1.0 1.5 0.5 3.26 3.27 3.28 3.29 3.30 3.31 3.32 3.33 3.34 3.35 3.25 0 v out2 = 2.5v at 0.75a v out3 = 12v at 25ma t ypical operating characteristics (circuit of max8513 evaluation kit, v in = 12v, t a = +25 c, f s = 1.4mhz, unless otherwise noted.)
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset 10 ______________________________________________________________________________________ max8513/14 toc12 200ns/div 0v 0v 0v 0v v dh 10v/div v dl 5v/div v lx 10v/div v d2 (anode) 20v/div switching waveforms (all outputs at full load) max8513/14 toc13 1 s/div 0v 0v 0v v dh 5v/div v dl 10v/div sync/en 5v/div synchronization max8513/14 toc14 2ms/div 0v 0v 0v v in 5v/div v out1 2v/div i out1 = 2a, i out2 = 1.5a, i out3 = 50ma pfo 2v/div pfo response max8513/14 toc15 100ms/div 0v 0v 0v 0v v out3 10v/div v out1 2v/div v out2 5v/div por 5v/div por response output1 load-transient response max8513/14 toc10 40 s/div 50mv/div 50mv/div 100mv/div 0a v out1 ac-coupled v out2 ac-coupled v out3 ac-coupled i out1 1a/div i out2 = 0.75a, i out3 = 25ma output3 load-transient response max8513/14 toc11 40 s/div 50mv/div 50mv/div 50mv/div 5ma v out1 ac-coupled v out2 ac-coupled v out3 ac-coupled i out3 50ma/div i out1 = 1a, i out2 = 0.75a t ypical operating characteristics (continued) (circuit of max8513 evaluation kit, v in = 12v, t a = +25 c, f s = 1.4mhz, unless otherwise noted.)
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset ______________________________________________________________________________________ 11 max8513/14 toc19 20 s/div 0a 0v 0v i l 2a/div v out1 2v/div v lx 10v/div output1 short circuit (all outputs at no load) -0.5 0.1 -0.1 -0.3 0.3 0.5 0.7 0.9 1.1 1.3 1.5 100 2100 1100 3100 4100 5100 output ripple and harmonics (measured at out1) max8513/14 toc20 frequency (khz) noise (mv) v in = 12v v out1 = 3.3v at 2a v out2 = 2.5v at 1.5a v out3 = 12v at 50ma max8513/14 toc16 2ms/div 0v 0v v out2 2v/div sync/en 5v/div v out3 5v/div v out1 2v/div staggered sequence (seq = gnd) max8513/14 toc17 4ms/div 0v 0v v out2 2v/div sync/en 5v/div v out3 5v/div v out1 2v/div tracking sequence (seq = vl) max8513/14 toc18 20 s/div 0a 0v 0v 1 l 2a/div v out1 2v/div v lx 10v/div output1 short circuit (all outputs at full load) t ypical operating characteristics (continued) (circuit of max8513 evaluation kit, v in = 12v, t a = +25 c, f s = 1.4mhz, unless otherwise noted.)
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset 12 ______________________________________________________________________________________ pin description pin name max8513 max8514 function pfi 1 1 power-fail input. connect pfi to an external resistive-divider between in, pfi, and gnd. pfi senses v in to detect voltage failure. trip falling threshold at this input is 1.22v, with 20mv of hysteresis. pfo 2 2 power-fail output. open-drain output that goes low if v pfi < 1.22v. dh 3 3 out1 high-side gate-drive output. dh drives the high-side n-channel mosfet (q1 in the typical applications circuits ). dh is a floating driver output that swings from lx to bst. lx 4 4 out1 high-side driver return path. the high-side fet driver uses bst and lx for its respective high and low-side supplies. bst 5 5 out1 boost capacitor connection for high-side gate drive. connect a 0.1? ceramic capacitor from bst to lx with a less than 5mm trace length. dl 6 6 out1 low-side gate-drive output. dl drives the low-side n-channel mosfet (q2 in the typical applications circuits ). dl swings from 0 to v pvl . pvl 7 7 out1 gate-drive supply bypass connection. connect pvl to vl through a 10 ? resistor (r15), and bypass pvl to pgnd with a minimum 1? capacitor (c1). pgnd 8 8 power-ground connection and low-side supply for dl driver vl 9 9 internal +5v linear-regulator bypass pin. bypass vl to gnd with a minimum 2.2? ceramic capacitor (c10) and 5mm or less of trace length. vl should be connected to in when v in < 5.5v. comp1 10 10 out1 compensation node. see the out1 compensation section. fb1 11 11 out1 feedback input. connect a resistive-divider (r1, r2) from out1 to fb1 to gnd to regulate fb1 at 1.25v. freq 12 12 oscillator frequency-set input. a resistor from freq to gnd sets the oscillator frequency from 300khz to 1.4mhz (f = 15mhz x k ? / r freq ). r freq is still required if an external clock is used at sync/en, and the sync/en input frequency should be within ?0% of the frequency set by r freq . ref 13 13 1.25v refer ence o utp ut. c onnect a 0.1f or l ar g er cer am i c cap aci tor ( c 9) fr om re f to gn d . gnd 14 14 analog/signal ground fb2 15 15 out2 feedback input. connect a resistive-divider (r5, r6) from out2 to fb2 to gnd to regulate fb2 to 0.8v. drv2 16 16 out2 gate drive. drv2 connects to the gate of an external n-channel mosfet to form a positive linear voltage regulator. sup2 17 17 supply input for drv2. connect to a voltage source of at least 1v above the maximum desired drv2 gate voltage.
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset ______________________________________________________________________________________ 13 pin description (continued) pin name max8513 max8514 function seq 18 18 connect to vl for output tracking. connect to gnd for output staggered sequence. staggered sequence ramps up v out2 and v out3 softly to avoid glitches on the previous voltage due to charging of the ldo? output capacitors. sync/en 19 19 shutdown control and synchronization input. there are three operating modes: ? when sync/en is low, the controller is off but the vl regulator is still running. ? when sync/en is high, the controller is enabled with the switching frequency set by r freq . ? when sync/en is driven by an external clock, the controller is enabled and switches at the external clock frequency. n.c. 20 no connection. not internally connected. connect to gnd or leave floating. sup3n 20 out3n base-drive supply. connect sup3n to any positive voltage between 1.5v and 5.5v to provide power for the negative linear-regulator transistor driver. drv3p 21 out3p base drive. connect drv3p to the base of an external pnp pass transistor to form a positive linear voltage regulator. drv3n 21 out3n base drive. connect drv3n to the base of an external npn pass transistor to form a negative linear voltage regulator. in 22 22 main voltage input (4.5v to 28v). bypass in to gnd, close to the ic, with a minimum 1? ceramic capacitor (c2). in powers the linear regulator whose output is vl. por 23 23 power-on reset. open-drain output that goes high after all outputs reach the regulation limit and a 315ms delay time has elapsed. fb3p 24 out3p feedback input. fb3p is referenced to 0.8v and connects to a resistive-divider (r13, r14) to control a positive linear voltage regulator. fb3n 24 out3n feedback input. connect a resistive-divider (r13, r14) from out1 to fb3n to out3n to regulate fb3n to 0v. ilim 25 25 ilim set input. connect a resistive-divider (r17, r18) from out1 to ilim to gnd. see the current limit section. csp 26 26 positive current-sense input. used to detect out1 current limit. csn 27 27 negative current-sense input. used to detect out1 current limit. ss 28 28 anal og s oft- s tar t c ontr ol inp ut. thi s p i n g oes i nto the p osi ti ve i np ut of the v ou t1 s er r or am p l i fi er . w hen the m ax 8513/m ax 8514 ar e tur ned on, s s i s at gn d and char g es up to 1.25v w i th a constant 25?. c onnect a cap aci tor ( c 13) fr om s s to g n d for the d esi r ed soft- star t ti m e.
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset 14 ______________________________________________________________________________________ max8513 n n reference n n error amp in ss sync/en vl gnd freq seq pfi ref fb3p drv3p fb2 drv2 sup2 ilim comp fb1 csn csp pgnd dl pvl lx dh bst pwm comp. bias 5 a 1/7.5 s r q q g c2 g c3p 1.25v 0.8v 0.8v 1v p-p pfo por figure 1. max8513 functional diagram
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset ______________________________________________________________________________________ 15 max8514 n n p p error amp in ss sync/en vl gnd freq seq pfi ref fb3n drv3n fb2 sup3n drv2 sup2 ilim comp fb1 csn csp pgnd dl pvl lx dh bst pwm comp. bias 5 a 1/7.5 s r q q g c2 g c3n 1.25v 0.8v 1v p-p pfo por reference figure 2. max8514 functional diagram
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset 16 ______________________________________________________________________________________ detailed description the max8513/max8514 combine a step-down dc-dc converter and two ldos, providing three output volt- ages for xdsl modem and set-top box applications. the switching frequency is set with an external resistor connected from the freq pin to gnd, and is adjustable from 300khz to 1.4mhz. the main step- down dc-dc controller operates in a voltage-mode, pulse-width-modulation (pwm) control scheme. the max8513/max8514 include two low-cost ldo con- trollers capable of delivering current from the dc-dc main output, an extra winding, the input, or from an alternate supply voltage. the first ldo controller drives an external nmos or npn with a maximum drive of 7.75v. the second ldo controller provides either a positive 0.8v to 27v output using an external pnp pass device, or a negative -1v to -18v output with an exter- nal npn pass device. dc-dc controller the max8513/max8514 step-down dc-dc converters use a pwm voltage-mode control scheme. an internal high-bandwidth (25mhz) operational amplifier is used as an error amplifier to regulate the output voltage. the output voltage is sensed and compared with an internal 1.25v reference to generate an error signal. the error signal is then compared with a fixed-frequency ramp by a pwm comparator to give the appropriate duty cycle to maintain output-voltage regulation. at the ris- ing edge of the internal clock and when dl (the low- side mosfet gate drive) is at 0v, the high-side mosfet turns on. when the ramp voltage reaches the error-amplifier output voltage, the high-side mosfet latches off until the next clock pulse. during the high- side mosfet on-time, current flows from the input through the inductor to the output capacitor and load. at the moment the high-side mosfet turns off, the energy stored in the inductor during the on-time is released to support the load. the inductor current ramps down through the low-side mosfet body diode. after a fixed delay, t he low-side mosfet turns on to shunt the current from its body diode for a lower voltage drop to increase the efficiency. the low-side mosfet turns off at the rising edge of the next clock pulse, and when its gate voltage discharges to zero, the high-side mosfet turns on after an additional fixed delay and another cycle starts. the max8513/max8514 operate in forced-pwm mode, so even under light load the controller maintains a con- stant switching frequency to minimize noise and possi- ble interference with system circuitry. current limit the max8513/max8514s?switching regulator senses the inductor current either through the dc resistance of the inductor itself for lossless sensing, or through a series resistor for more accurate sensing. when using the dc resistance of the inductor, an rc filter circuit is needed (see r19, r20, and c14 of the typical applications circuits and the current-limit setting sec- tion). when peak voltage across the sensing circuit (which occurs at the peak of the inductor current) exceeds the current-limit threshold set by ilim, the controller turns off the high-side mosfet and turns on the low-side mosfet. the inductor current ramps down and dh turns on again if the inductor current is below the current-limit threshold at the next clock pulse. the max8513/max8514 current-limit threshold can be set by two external resistors to be proportional to the output voltage with an adjustable offset level, providing foldback current-limit and short-circuit pro- tection. this feature greatly reduces power dissipation and prevents overheating of external components dur- ing an indefinite short-circuit at the output. see the foldback current limit section for how to set ilim with external resistors. the current-limit threshold defaults to 170mv when ilim is connected to vl, and in this case, the current limit functions as a constant current limit only. the ldo controllers do not have current limit and rely on input current limit for protection. synchronous-rectifier driver (dl) synchronous rectification reduces the conduction loss in the rectifier by replacing the normal schottky catch diode with a low-on-resistance mosfet switch. the max8513/max8514 also use the synchronous rectifier to ensure proper startup of the boost gate-drive circuit. high-side gate-drive supply (bst) a flying-capacitor boost circuit (see d1 and c3 in the typical applications circuits ) generates the gate-drive voltage for the high-side n-channel mosfet. on start- up, the synchronous rectifier (low-side mosfet, q2) forces lx to ground and charges the boost capacitor (c3) to v vl - v diode . on the second half-cycle, the controller turns on the high-side mosfet by closing an internal switch between bst and dh. this boosts the voltage at bst to v vl - v diode + v in , providing the necessary gate-to-source voltage to turn on the high- side n-channel mosfet.
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset ______________________________________________________________________________________ 17 internal 5v linear regulator all max8513/max8514 functions (except for the posi- tive output ldo with an nfet or npn, and the negative ldo on the max8514) are powered from the on-chip low-dropout 5v regulator with its input connected to in. bypass the regulator? output (vl) with a 2.2? or greater ceramic capacitor. the v in to v vl dropout volt- age is typically 350mv, so when v in is greater than 5.5v, v vl is typically 5v. if v in is between 4.5v and 5.5v, short vl to in. undervoltage lockout if v vl drops below 3.8v, the max8513/max8514 assume that the supply voltage is too low to make valid decisions. when this happens, the undervoltage lock- out (uvlo) circuitry inhibits switching, forces por and pfo low, and forces dl and dh gate drivers low. after v vl rises above 3.9v, the controller powers up the out- puts (see the startup section). startup the max8513/max8514 start switching when v vl rises above the 3.9v uvlo threshold. however, the con- troller is not enabled unless all three of the following conditions are met: 1) v vl exceeds the 3.9v uvlo threshold. 2) the internal reference exceeds 90% of its nominal value. 3) the thermal limit is not exceeded. once the max8513/max8514 assert the internal enable signal, the step-down controller starts switching and enables soft-start. the soft-start circuitry gradually ramps up to the reference voltage to control the rate-of-rise of the step-down controller and reduce input surge cur- rents. the soft-start period is determined by the value of the capacitor from ss to gnd (c13 in the typical applications circuits ). ss sources a constant 25a to charge the soft-start capacitor to 1.25v. output-voltage sequencing the max8513/max8514 can power up in either stag- gered-output sequencing or output tracking. for stag- gered-output sequencing, connect seq to gnd. in this configuration, v out1 comes up first. when it reaches 90% of the nominal regulated value, v out2 is softly turned on. once v out2 reaches 90% of its nominal regu- lated value, v out3 is softly turned on. individual soft-start on out2 and out3 eliminates glitches on the previous stages due to the charging of output capacitors. see the typical operating characteristics section for the startup and staggered-output-sequence waveforms. output-voltage tracking when seq is connected to vl, all outputs rise up at the same time and the external series pass transistors are driven fully on until reaching the respective regulation limits. since the ldos are powered from the main dc- dc step-down converter, either directly or through a coupled winding on the inductor, their outputs track the dc-dc step-down output (out1). see the typical operating characteristics section for the startup output- tracking waveforms. power-on reset the max8513/max8514 provide a power-on-reset ( por ) signal, which goes high 315ms after all outputs reach 90% of their nominal regulated value. therefore, by the time por goes high, all outputs are already stabilized at nominal regulated voltages. see the typical operating characteristics section for the por waveforms. input power-fail (pfi and pfo) the max8513/max8514 have a built-in comparator to detect the input voltage with an external resistive- divider at pfi, with a threshold of 1.22v. when the input voltage drops and trips this comparator, the power-fail output ( pfo ) goes low, while all outputs are still within regulation limits. this is typically used for input power- fail warning for orderly system shutdown. the amount of warning time depends on the input storage capacitor, the input pfi trip voltage level, the main step-down out- put voltage, the total output power, and the efficiency. see the design procedure section for how to calculate the input capacitor to meet the required warning time. enable and synchronization the max8513/max8514 can be turned on with logic high, and off with logic low at sync/en. when sync/en is driven with an external clock, the internal oscillator synchronizes the rising edge of the clock at sync/en to dh going high. when being driven by a synchronization clock signal at sync/en, the controller synchronizes to the external clock within two cycles. the frequency at sync/en needs to be within ?0% of the value set by r freq . see the switching-frequency setting section.
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset 18 ______________________________________________________________________________________ thermal-overload protection thermal-overload protection limits the total power dissi- pation in the max8513/max8514. when the junction temperature exceeds t j = +170?, a thermal sensor shuts down the device, forcing dl and dh low and allowing the ic to cool. the thermal sensor turns the part on again after the junction temperature cools by 25?, resulting in a pulsed output during continuous thermal- overload conditions. during a thermal event, the main step-down converter and the linear regulators are turned off, por and pfo go low, and soft-start is reset. design procedure out1 voltage setting the output voltage is set by a resistive-divider network from out1 to fb1 to gnd (see r1 and r2 in the typical applications circuits ). select r2 between 5k ? and 15k ? . then r1 can be calculated by: input power-fail setting the pfi input can monitor v in to determine if it is falling. when the voltage at pfi crosses 1.22v, the output ( pfo ) goes low. the input voltage value at the pfi trip threshold, v pfi , is set by a resistive-divider network from in to pfi to gnd (see the typical applications circuits ). select r11, the resistor from pfi to gnd between 10k ? and 40k ? . then r10, the resistor from pfi to in, is calculated by: switching-frequency setting the resistor connected from freq to gnd, r freq (r7 in the typical applications circuits ), sets the switching frequency, f s , as shown by the equation below: where r freq is in ohms. inductor value there are several parameters that must be examined when determining which inductor to use: input voltage, output voltage, load current, switching frequency, and lir. lir is the ratio of peak-to-peak inductor ripple cur- rent to the maximum dc load current. a higher lir value allows for a smaller inductor but results in higher losses and higher output ripple. a good compromise between size and efficiency is a 30% lir. once all of the parameters are chosen, the inductor value is deter- mined as follows: where v out1 is the main switching regulator output and f s is the switching frequency. choose a standard value close to the calculated value. the exact inductor value is not critical and can be adjusted to make tradeoffs between size, cost, and effi- ciency. lower inductor values minimize size and cost, but also increase the output ripple and reduce the effi- ciency due to higher peak currents. on the other hand, higher inductor values increase efficiency, but eventual- ly resistive losses due to extra turns of wire exceed the benefit gained from lower ac current levels. find a low- loss inductor with the lowest possible dc resistance that fits the allotted dimensions. ferrite cores are often the best choice, although powdered iron is inexpensive and can work well up to 300khz. the chosen inductor? satu- ration current rating must exceed the peak inductor cur- rent as calculated below: this peak value should be smaller than the value set at ilim when v out1 is at its nominal regulated voltage (see the current limit and current-limit setting sections). in applications where a multiple winding inductor (cou- pled inductor) is used to generate the supply voltages for the ldos, the inductance value calculated above is for the winding connected to the dc-dc step-down (primary windings) inductance. the inductance seen from the other windings (secondary windings) is pro- portional to the square of the turns ratio with respect to the primary winding. the turns ratio is important since it sets the ldos?sup- ply voltage values. the voltage generated by the sec- ondary winding (v sec ) together with the rectifier diode and output capacitor is calculated as follows: where v q2 and v d2 are the voltage drops across the low-side mosfet on the primary side and the rectifier vvv n n sec out q =+ () ? ? ? ? ? ? 12 2 1 - v d2 ii vv lf v peak out max in out sin _ =+ () 1 1 2 - v out1 l vvv vfi lir out in out in s out max _ = () 11 1 - f r hz s freq = 15 10 9 ? rr v v pfi 10 11 122 1 . = ? ? ? ? ? ? - rr v v out 12 125 1 1 . = ? ? ? ? ? ? -
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset ______________________________________________________________________________________ 19 diode on the secondary side (q2 and d2 in the typical applications circuits ). n 2 and n 1 are the number of turns of the secondary winding and the primary wind- ing, respectively. it is important to have the secondary winding tightly coupled with the primary winding to minimize leakage inductance for higher efficiency. the positive voltage generated by the secondary winding can also be stacked with the main dc-dc step-down converter out- put to further improve efficiency and reduce winding cost. in this case, the secondary-side voltage is: input capacitor the input-filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on the input caused by the ac-rms current through the esr of the input capacitor (c2 in the typical applications circuits ). the input capacitor must meet the ripple-current requirement (i in_rms ) imposed by the switching currents defined by the following equation: i in_rms has a maximum value when the input voltage equals twice the output voltage (v in = 2 v out1 ), so i in_rms(max) = i out1 / 2. ceramic capacitors are rec- ommended due to their low esr and esl at high fre- quency, with relatively low cost. choose a capacitor that exhibits less than 10 c temperature rise at the maximum operating rms current for optimum long-term reliability. for applications that require input power-fail warning, such as dying gasp, add a large-value electrolytic capacitor (c s ) to the input as a local energy storage device to provide the power to the converter in case of input power-fail. the capacitor value must be high enough to meet the desired power-fail warning time, t warn , where t warn is the time from when pfi trips the pfo output to when the main output (out1) starts dropping out of regulation. the value of the storage capacitor, c s , can be calculated as: where p out1 is the total output power, is the total converter efficiency, v pfi is the input voltage value at the input power-fail (pfi) trip threshold, and v droop is the input voltage value where v out1 starts dropping out of regulation. v pfi and v droop can be calculated as: where r10 and r11 are the resistive-dividers from in to pfi to gnd in the typical applications circuits . where d max is the maximum duty cycle. to ensure for worst-case component tolerances such as capacitance of c s , converter efficiency, v pfi , and v droop ? threshold over the operating temperature range, it is recommended to select c s at least 1.5 times the calculated value above. output capacitor the key selection parameters for the output capacitor are the actual capacitance value, the equivalent series resistance (esr), the equivalent series inductance (esl), and the voltage-rating requirements. all of these affect the overall stability, output ripple voltage, and transient response. the output ripple is composed of three components: vari- ations in the charge stored in the output capacitor, the voltage drop across the capacitor? equivalent series resistance (esr), and equivalent series inductance (esl) caused by the current into and out of the capacitor. v v d droop out max = 1 vv r r pfi . =+ ? ? ? ? ? ? 122 1 10 11 c p t v s out warn pfi . = ? ? ? ? ? ? ? ? ? ? ? ? () 05 1 1 v - 1 v - v pfi droop droop i ivvv v in rms out out in out in _ = () 11 1 - vvv n n v sec out q out =+ () ? ? ? ? ? ? 12 2 1 1 +- v d2
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset 20 ______________________________________________________________________________________ the peak-to-peak output voltage ripple as a conse- quence of the esr, esl, and output capacitance is: where c out is c4 in the typical applications circuits . where i p-p is the peak-to-peak inductor current (see the inductor selection section). an approximation of the overall voltage ripple at the output is: while these equations are suitable for initial capacitor selection to meet the ripple requirement, final values may also depend on the relationship between the lc double- pole frequency and the capacitor esr zero. generally, the esr zero is higher than the lc double pole (see the compensation design section). solid polymer electrolyt- ic or ceramic capacitors are recommended due to their low esr and esl at higher frequencies. higher output current may require paralleling multiple capacitors to meet the output voltage ripple. the max8513/max8514s?response to a load transient depends on the selected output capacitor. after a load transient, the output instantly changes by (esr ? i out1 ) + (esl di out1 / dt). before the controller can respond, the output deviates further depending on the inductor and output capacitor values. after a short peri- od of time (see the typical operating characteristics ), the controller responds by regulating the output voltage back to its nominal state. the controller response time depends on the closed-loop bandwidth. with a higher bandwidth the response time is faster, preventing the output capacitor from further deviation from its regulat- ing value. be sure not to exceed the capacitor? voltage or current ratings. mosfet selection the max8513/max8514 drive two external, logic-level, n-channel mosfets as the circuit switch elements. the key selection parameters are: for on-resistance (r ds_on ), the lower the better. maximum drain-to-source voltage (v ds ) should be at least 20% higher than the input supply rail at the high-side mosfet? drain. for gate charges (q gs , q gd , q ds ), the lower the better. choose the mosfets with rated r ds_on at v gs = 4.5v. for a good compromise between efficiency and cost, choose the high-side mosfet (q1 in the typical applications circuits ) that has conduction loss equal to switching loss at nominal input voltage and maximum output current. for the low-side mosfet (q2 in the typical applications circuits ), make sure that it does not spuriously turn on due to dv/dt caused by q1 turn- ing on as this results in shoot-through current degrad- ing the efficiency. mosfets with a lower q gd / q gs ratio have higher immunity to dv/dt. for proper thermal management, the power dissipation must be calculated at the desired maximum operating junction temperature, maximum output current, and worst-case input voltage. for q2, the worst case is at v in_max . for q1, it could be either at v in_min or v in_max . q1 and q2 have different loss components due to the circuit operation. q2 operates as a zero volt- age switch, where major losses are the channel con- duction loss (p q2cc ) and the body-diode conduction loss (p q2dc ). where v f is the body-diode forward voltage drop, t dt = 50ns is the dead time between q1 and q2 switching transitions, and f s is the switching frequency. the total losses for q2 are: q1 operates as a duty-cycle control switch and has the following major losses: the channel conduction loss (p q1cc ), the v i overlapping switching loss (p q1sw ), and the drive loss (p q1dr ). q1 does not have body- diode conduction loss because the diode never con- ducts current. where r ds_on is at the maximum operating junction temperature. p v v ir qcc out in out ds on 1 1 1 2 _ = ppp q total q cc q dc 222 _ =+ p v v ir pivtf qcc out in out ds on qdc out f dt s 2 1 1 21 1 2 2 = ? ? ? ? ? ? = _ - vv v v ripple ripple c ripple esr ripple esl =+ + () ( ) ( ) v v esl la esl and i vv fl v v ripple esl in pp in out s out in () = + = ? ? ? ? ? ? ? ? ? ? ? ? 1 11 - - vir v i cf ripple esr p p esr ripple c pp out s () () = = - - 8
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset ______________________________________________________________________________________ 21 where i gate is the average dh high driver output-cur- rent capability determined by: where r dh is the high-side mosfet driver? on-resis- tance (1.5 ? typ) and r gate is the internal gate resis- tance of the mosfet ( 2 ? ). where v gs v vl = 5v. the total power loss in q1 is: in addition to the losses above, allow approximately 20% more for additional losses due to mosfet output capacitances and q2 body-diode reverse recovery charge dissipated in q1. this is not typically well- defined in mosfet data sheets. refer to the mosfet data sheet for the thermal-resistance specification to calculate the pc board area needed to maintain the desired maximum operating junction temperature with the above calculated power dissipations. to reduce emi caused by switching noise, add a 0.1? or larger ceramic capacitor from the high-side mosfet drain to the low-side mosfet source or add resistors in series with dh and dl to slow down the switching transitions. however, adding series resistors with dh and dl increases the power dissipation in the mosfet when it switches, so be sure this does not overheat the mosfet. the minimum load current must exceed the high-side mosfet? maximum leakage current over temperature if fault conditions are expected. mosfet snubber circuit fast switching transitions cause ringing because of res- onating circuit parasitic inductance and capacitance at the switching nodes. this high-frequency ringing occurs at lx? rising and falling transitions and can interfere with circuit performance and generate emi. to dampen this ringing, a series-rc snubber circuit is added across each switch. the following is the proce- dure for selecting the value of the series-rc circuit: 1) connect a scope probe to measure v lx to gnd, and observe the ringing frequency, f r . 2) find the capacitor value (connected from lx to gnd) that reduces the ringing frequency by half. the circuit parasitic capacitance (c par ) at lx is then equal to 1/3rd the value of the added capacitance above. the circuit parasitic inductance (l par ) is calculated by: the resistor for critical dampening (r snub ) is equal to (2 f r l par ). adjust the resistor value up or down to tailor the desired damping and the peak voltage excur- sion. the capacitor (c snub ) should be at least 2 to 4 times the value of the c par to be effective. the power loss of the snubber circuit is dissipated in the resistor (p rsnub ) and can be calculated as: where v in is the input voltage and f s is the switching frequency. choose an r snub power rating that meets the specific application? derating rule for the power dissipation calculated. current-limit setting the max8513/max8514 can provide foldback current limit or constant current limit. unless constant current- limit operation is required, such as when driving a con- stant current load, foldback current limit should be implemented. foldback current limit reduces the power dissipation of external components under overload or short-circuit conditions. foldback current limit for foldback current limit, the current-limit threshold is set by an external resistive-divider from v out1 to ilim to gnd (r17 and r18 of the typical applications circuits ). this makes the voltage at ilim a function of the internal 5? current source and v out1 . the current-limit com- parator threshold is equal to v ilim / 7.5. this threshold is compared with v sense . v sense is either the voltage across the current-sense resistor or, for lossless sens- ing, the voltage across the inductor. when v sense exceeds the current-limit threshold, the high-side mosfet turns off and the low-side mosfet turns on. this allows for a current foldback feature that reduces the current-limit threshold during a short circuit. this makes the current threshold limit, when v out = 0v, a percentage of the current-limit threshold, when v out1 is at its nominal regulated value. pc vf rsnub snub in s = () 2 l fc par r par = () 1 2 2 pp p p qqcc qs wqdr 11 1 1 =+ + pqvf r rr qdr gs gs s gate gate dh 1 = + () i v rr gate dh gate = + () 25 . pvi f qq i qsw in out s gs gd gate 11 = + ()
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset 22 ______________________________________________________________________________________ to set the current limit and the current-limit foldback thresholds, first select the foldback current-limit ratio (p fb ) . this ratio is the foldback current limit (i limit@0v ) divided by the current limit when v out1 equals its nom- inal regulated voltage (i limit ). p fb is typically set to 0.5. to calculate the values of r17 and r18 (in the typical applications circuits ), use the following equations: r cs_max is the maximum sensing resistance at the high operating temperature. r cs can either be the series resistance of the inductor or a discrete current- sense resistor value. i limit is the peak inductor current at maximum load, which equals: if r18 results in a negative resistance, then decrease r cs . this can be done by choosing an inductor with a lower dc resistance or a lower value discrete current- sense resistor. constant current limit for constant current-limit operation, connect ilim to vl for a default current-limit threshold of 170mv (typ). the sensing resistor value must then be chosen so that: r cs_max i limit < 151mv the minimum value of the default threshold. alternately, the constant current-limit threshold can also be set by using only r18, in which case r18 is calculat- ed as follows: when using the dc resistance of the inductor as a cur- rent-sense resistor, an rc filter is needed (r19 and c14 of the typical applications circuits ). pick the value of the filter capacitor, c14, from 0.22? to 1? (ceramic x7r). then calculate the value of r19 as follows: r l_dc is the nominal value of the inductor? dc resis- tance. additionally, r20 (in the typical applications circuits ) is added in series with the csn input to cancel the drop due to input bias current into csp that devel- ops across r19. r20 should be set equal to r19. compensation design the max8513/max8514 use a voltage-mode control scheme that regulates the output voltage by comparing the error-amplifier output (comp) with a fixed internal ramp to produce the required duty cycle. the output lowpass lc filter creates a double pole at the resonant frequency, which has a gain drop of -40db/decade and a phase shift of approximately -180 /decade. the error amplifier must compensate for this gain drop and phase shift to achieve a stable high-bandwidth closed- loop system. the basic regulator loop consists of a power modulator, an output feedback divider, and an error amplifier. the power modulator has a dc gain set by v in / v ramp (v ramp = 1v p-p ), with a double pole and a single zero set by the output inductance (l), the output capaci- tance (c out ) (c4 in the typical applications circuits ), and its equivalent series resistance (r esr ). v ramp is the peak of the saw-toothed waveform at the input of the pwm comparator (see the functional diagrams in figures 1 and 2). below are equations that define the power modulator: where l is l1a and c out is c4 in the typical applica- tions circuits . f cr zesr out esr = 1 2 g v v f lc mod dc in ramp pmod out () = = 1 2 r la rc ldc 19 1 214 _ = () rr i a cs max limit 18 7 5 47 . . _ = i lir out max 1 1 2 _ + ? ? ? ? ? ? r pv ap r ripr vrip fb out fb cs max limit fb out cs max limit fb 17 47 1 18 75 1 17 75 1 1 1 = () () = () () () () . . . _ _ - - -- p i i fb limit v limit = @0
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset ______________________________________________________________________________________ 23 when the output capacitance is comprised of parallel- ing n number of identical capacitors whose values are c each with esr of r esr_each , then: thus the resulting f zesr is the same as that of each capacitor. the crossover frequency (f c ), which is the frequency when the closed-loop gain is equal to unity, should be the smaller of 1/5th the switching frequency or 100khz (see the switching-frequency setting section): the loop-gain equation at the crossover frequency is: where g ea(fc) is the error-amplifier gain at f c , and g mod( f c) is the power modular gain at f c . the loop compensation is affected by the choice of out- put-filter capacitor used, due to the position of its esr zero frequency with respect to the desired closed-loop crossover frequency. ceramic capacitors are used for higher switching frequencies (above 750khz) because of low capacitance and low esr; therefore, the esr zero frequency is higher than the closed-loop crossover frequency. while electrolytic capacitors (e.g., tantalum, solid polymer, oscon, etc.) are needed for lower switch- ing frequencies, because of high capacitance and esr, the esr zero frequency is typically lower than the closed-loop crossover frequency. thus the compensa- tion design procedure is separated into two cases: case 1: ceramic output capacitor (operating at high switching frequencies, f zesr > f c ) the modulator gain at f c is: since the crossover frequency is lower than the output capacitors?esr zero frequency and higher than the lc double-pole frequency, the error-amplifier gain must have a +20db/decade slope at f c . this +20db/decade slope of the error amplifier at crossover then adds to the -40db/decade slope of the lc double pole, and the resultant compensated loop crosses over at the desired -20db/decade slope. the error amplifier has a dominant pole at very low frequency ( 0hz), and two separate zeros at: and poles at: the error-amplifier equivalent circuit and its gain vs. frequency plot are shown below in figure 3. in this case, f z2 and f p1 are selected to have the convert- ers?closed-loop crossover frequency, f c , occur when the error-amplifier gain has a +20db/decade slope between f z2 and f p2 . the error-amplifier gain at f c is: the gain of the error amplifier between f z1 and f z2 is: gg f f f fg ea fz fz ea fc z c z c mod fc () () () 12 22 - == g g ea fc mod fc () () = 1 f rc and f r cc cc pp 23 1 2411 1 23 512 512 = = + ? ? ? ? ? ? f rc and f rr c zz 12 1 235 1 21411 = = + () gg f f mod fc mod dc pmod c () ( ) = ? ? ? ? ? ? 2 gg ea fc mod fc () () = 1 f f or khz c s 5 100 cnc and r r n out each esr esr each _ = = figure 3. case 1: error-amplifier compensation circuit (closed- loop and error-amplifier gain plot) ref r1 r3 r4 c12 c5 c11 comp r2 ea v out1 gain (db) frequency f p3 f p2 f z1 f z2 f c closed-loop gain ea gain
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset 24 ______________________________________________________________________________________ this gain is also set by the ratio of r3/r1 where r1 is calculated in the out1 voltage setting section. thus: due to the underdamped (q > 1) nature of the output lc double pole, the error-amplifier zero frequencies must be set less than the lc double-pole frequency to provide adequate phase boost. set the error-amplifier first zero, f z1 , at 1/4th the lc double-pole frequency and the second zero, f z2 , at the lc double-pole frequency. hence: set the error-amplifier f p2 at f zesr , and f p3 to 1/2 the switching frequency, if f zesr < 1/2 f s . if f zesr > 1/2 f s , then set f p2 at 1/2 f s and f p3 at f zesr . the gain of the error amplifier between f p2 and f p3 is set by the ratio of r3/r i and is equal to: where r i is the parallel combination of r1 and r4 and is equal to: therefore: c11 can then be calculated as: and c12 as: below is a numerical example to calculate the error- amplifier compensation values used in the typical applications circuit of figure 5: v in = 12v (nomimal input voltage) v ramp = 1v v out1 = 3.3v v fb1 = 1.25v l1a = 1.8? c4 = 47?/ 6.3v ceramic, with r esr = 0.008 ? f s = 1.4mhz the lc double-pole frequency is calculated as: pick r2 = 8.06k ? . the modulator gain at dc is: pick f c = 100khz. g khz khz g f fg khz khz rrg kk mod fc ea fz fz pmod c mod fc ea fz fz () () () () . . . . . . . . = ? ? ? ? ? ? = = = = = == ? ? 12 17 4 100 0 363 17 4 100 0 363 0 479 31 13 3 0 479 6 37 2 12 12 ?? g v v mod dc in ramp () == 12 rk v v k 1806 33 125 1133 . . . . = ? ? ? ? ? ? = ?? - f la c khz f rc khz pmod zesr esr . . . = = = = = = 1 21 4 1 21810 4710 17 3 1 24 1 20 008 47 10 423 66 6 -- - c c crf p 12 5 253 3 = () -1 c rf p 11 1 24 2 = r rf fg and r rr rr i pmod peafzfz i i () = = 3 4 1 1 212 - - r rr rr i = + 14 14 r r g f f i ea fz fz p pmod 3 12 2 () = - c rf pmod 5 2 3 = r rf fg z c mod fc 3 1 2 () =
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset ______________________________________________________________________________________ 25 use 6.8k ? . use 4.7nf. use 620 ? . use 680pf. pick f p3 = 700khz, which is the midpoint between f zesr and 1/2 the switching frequency. use 33pf. case 2: electrolytic output capacitor (operating at lower switching frequencies, f zesr < f c ) the modulator gain at f c is: the output capacitor? esr zero frequency is higher than the lc double-pole frequency but lower than the closed-loop crossover frequency. here the modulator already has a -20db/decade slope; therefore, the error- amplifier gain must have a 0db/decade slope at f c , so the loop crosses over at the desired -20db/decade slope. the error-amplifier circuit configuration is the same as case 1; however, the closed-loop crossover frequency is now between f p2 and f p3 , as illustrated in figure 4. the equations that define the error amplifier? poles and zeroes (f z1 , f z2 , f p2 , and f p3 ) are the same as for case 1. however, f p2 is now lower than the closed-loop crossover frequency. the error-amplifier gain at f c is: and the gain of the error amplifier between f z1 and f z2 is: due to the underdamped (q > 1) nature of the output lc double pole, the error-amplifier zero frequencies must be set less than the lc double-pole frequency to provide adequate phase boost. set the first zero of the error amplifier, f z1 , at 1/4th the lc double-pole frequency. set the second zero, f z2 , at the lc double-pole frequency. set the second pole, f p2 , at f zesr . gg f f f fg ea fz fz ea fc z p z p mod fc () () () 12 2 2 2 2 ? == g g ea fc mod fc () () = 1 gg f ff mod fc mod dc pmod zesr c () ( ) = 2 c c crf nf nf k khz pf p 12 5 253 47 247 6 8 700 33 7 3 = = = () . (. . ) . -1 -1 ? c rf khz pf p 11 1 24 1 2 620 423 607 2 = = = ? r rf fg k khz khz r rr rr k k i pmod peafzfz i i . . . . . () = = = = = = 368174 423 0 479 583 4 1 1 13 3 583 13 3 583 609 212 - -- ? ? ?? ?? ? c rf k khz nf pmod 5 2 3 2 68 17 4 538 .. . = = = ? figure 4. case 2: error-amplifier compensation circuit (closed- loop and error-amplifier gain plot) v ref r1 r3 r4 c12 c5 c11 v comp r2 ea v out1 gain (db) frequency f p3 f p2 f z1 f z2 f c closed-loop gain ea gain
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset 26 ______________________________________________________________________________________ this gain between f z1 and f z2 is also set by the ratio of r3/r1, where r1 is selected in the out1 voltage setting section. therefore: and similar to case 1, c5 can be calculated as: set the error-amplifier third pole, f p3 , at approximately 1/2 the switching frequency. the gain of the error amplifier at f c (between f p2 and f p3 ) is set by the ratio of r3/r i and is also equal to: where r i is: therefore: similar to case 1, r4, c11, and c12 can be calculated as: below is a numerical example to calculate the error- amplifier compensation values for case 2: v in = 12v (nomimal input voltage) v ramp = 1v v out1 = 3.3v v fb1 = 1.25v l1a = 6.2? c4 = 560?/ 10v os-con capacitor, with esr = 0.015 ? f s = 300khz pick r2 = 8.06k ? . then: pick f c = 50khz, which is less than f s / 5. use 20k ? . use 12nf. use 2.2k ? . use 3.9nf. pick f p 3 = f s / 2 = 150khz. c rf k khz nf zesr 11 1 24 1 222 1895 382 .. . = = = ? rr g k k r rr rr kk kk k i mod fc i i .. .. .. . () = = = = = = 32 00 0923 1 846 4 1133 1 846 13 3 1 846 214 ?? ?? ?? ? 1- - c rf k khz nf pmod 5 2 3 2 20 2 7 11 8 . . = = = ? g khz khz khz g f fg khz khz rrg k k mod dc ea fz fz pmod zesr mod fc ea fz fz () () () () . . . . .. . .. . = = = = = = = = ? 12 27 18 95 50 0 0923 27 18 95 0 0923 1 543 31 1331 543 20 48 2 12 12 - ?? rk v v k g v v mod dc in ramp 1806 33 125 1133 12 . . . . () = = == ?? - f la c hf khz f rc f khz pmod zesr esr = = = = = = . . . . 1 21 4 1 262 560 27 1 24 1 20 015 560 18 95 ? ? r rr rr c rf c c crf i i zesr p 4 1 1 11 1 24 12 5 253 1 3 = = = - - rr g g i mod fc d () = 3 r rr rr i = + 14 14 g g ea fc mod fc () () = 1 c rf pmod 5 2 3 = r rf fg pmod zesr mod fc 3 1 () =
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset ______________________________________________________________________________________ 27 use 47pf. linear-regulator controllers out2 voltage selection the max8513/max8514 out2 positive linear regula- tor? output voltage is set by connecting a resistive- divider from out2 to fb2 to gnd. the resistors in the divider are selected to set the minimum output current (i out2_min ). for the typical applications circuit (figure 5 or figure 6), the feedback resistors are set to r5 = 340 ? and r6 = 160 ? , where r5 is the resistor from out2 to fb2 and r6 is the resistor from fb2 to gnd. these values set the minimum output current to 4.5ma, which works well with many mosfets. in general, select r5 and r6 so: out2 stability a transconductance amplifier drives the gate of the nmos transistor (q3 in the typical applications circuits ), with current proportional to the error signal multiplied by the amplifier? transconductance. the error signal is the difference between v fb2 and the internal 0.8v reference. v sup2 , the supply voltage for the transconductance amplifier, must be at least 1v greater than the maximum required gate voltage (v drv2 ). the output pass transistor (q3) buffers the drv2 signal to produce the desired output voltage (v out2 ). the output capacitor (c6 in the typical applications circuits ) helps bypass the output, while the feedback resistors (r5 and r6) set the output-volt- age reference point as well as the minimum load. the loop gain for the positive ldo output using an nmos transistor is: where c out2 is c6 in the typical applications circuits . g c2 is the transconductance of the internal amplifier (0.21s typ), and a dominant pole at a low frequency is created from this transconductance and the compen- sation capacitor (c a in the typical applications circuits + q3? gate capacitance (c q )). a second pole occurs due to c out2 and the transconductance of q3 (g c ). this transconductance varies from a minimum g c(min) occurring at minimum load to a maximum g c(max) occurring at maximum load. to calculate the g c at any load current, the typical forward transconductance can be extracted from the mosfet? data sheet (gfs), as well as the current at which it is measured (idfs). the g c(min) and g c(max) can be calculated as: poles occur at: if only a minimum gfs is given, initially assume the max- imum is twice the minimum. when using a bipolar transistor, the g c(max) and g c(min) occur at the following: where v t is the thermal voltage, 26mv. g i v g i v c min out min t c max out max t () () = = 2 2 f g c and f g c pmax c max out pmin c min out () () = = 2 2 2 2 g gfs i idfs g gfs i idfs c max out max c min out min () () () () = = 2 2 08 1 11 2 2 2 .v v g sca ra sca cq sc g sra cq out c out c + () + () + ? ? ? ? ? ? + () rr v v out 56 08 1 2 . = ? ? ? ? ? ? - 08 6 2 . _ v r i out min = i i out min out max 2 2 333 _ _ = c c crf nf nf k khz pf p 12 5 253 1 12 212 20 150 1 53 3 3 = = = () . - - ?
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset 28 ______________________________________________________________________________________ a third pole occurs due to the input capacitance of the nmos transistor? gate, c q (c iss from the mosfet data sheet), and the compensation resistor (r a ). if an npn bipolar transistor is used instead, this third pole can be calculated from the base capacitance (c q = c ibo from the npn data sheet). to ensure stability, a zero is added to the loop from the resistor (r a ) and capacitor (c a ). for good stability and transient response, first pick c out2 at approximately 6.8?/a of load current. for the typical applications circuit , c out2 is a 10? ceramic capacitor. ensure that the zero formed from the esr of c out2 is greater than the maximum bandwidth bw max (calculated below). the maximum bandwidth should also be less than the pole created by q3? gate capaci- tance (cq) and the compensation resistor (r a ). the following equations set the compensation zero a decade and a half below the maximum load pole and ensure the above constraint is met. choose the larger of the two values for c a . mosfet transistor selection max8513/max8514s?out2 uses n-channel mosfets as the series pass transistor to improve efficiency for high output current by not requiring a large amount of drive current. the selected mosfet must have the gate threshold voltage meet the following criteria: where v drv2 is equal to 7.75v or v sup2 - 1.5v (whichever is less), and v gsmax is the maximum gate voltage required to yield the on-resistance specified by the manufacturer? data sheet. logic-gate mosfets are recommended. npn-transistor selection the max8513/max8514s?out2 can use a less expen- sive npn transistor as the series pass transistor. in selecting the appropriate npn transistor, make sure the beta is large enough so the regulator can provide enough base current. the minimum beta of the transis- tor is: in addition, to avoid premature dropout, v ce_sat v in_min - v out2 . out3_ transistor selection the pass transistors must meet specifications for cur- rent gain ( ), input capacitance, collector-emitter satu- ration voltage, and power dissipation. the transistor? current gain limits the guaranteed maximum output cur- rent to: where i drv3p_min is the minimum base-drive current and r12 is the pullup resistor connected between the transistor? base and emitter (see the typical applications circuits ). in addition, to avoid premature dropout v ce_sat v in_min - v out3 . furthermore, the transistor? current gain increases the linear regulator? dc loop gain (see the stability requirements section), so excessive gain destabilizes the output. therefore, transistors with current gain over 100 at the maximum output current, such as darlington transistors, are not recommended. the transistor? input capacitance and input resistance also create a second pole, which could be low enough to destabilize the ldo when the output is heavily loaded. the transistor? saturation voltage at the maximum output current determines the minimum input-to-output voltage differential that the linear regulator supports. alternately, ii out p drv p min 33 _ = ? ? ? ? ? ? -- v r12 be () () min out max i ma = 2 4 vvv gs max drv out _ 22 - r vc c gr gv i a out out a c max esr cout c max out out max = + + 10 10 1 22 2 22 () () () _ () () c max vc cgg gr gv i gg gv i rcc a out out q c c max c max esr cout c max out out max cc max c max out out max esr cout out q = + () + + () ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 13 8 1 16 10 2 2 22 2 22 2 () () _ () () () () () _ , bw min cr rc max gc esr cout out = ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 13 1 2 1 10 1 2 2 . , _
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset ______________________________________________________________________________________ 29 the package? power dissipation could limit the useable maximum input-to-output voltage differential. the maximum power-dissipation capability of the tran- sistor? package and mounting must allow the actual power dissipation in the device without exceeding the maximum junction temperature. the power dissipated equals the maximum load current multiplied by the maximum input-to-output voltage differential. when the max8513/max8514 are disabled, r26 dis- charges c7. out3p voltage selection (pnp) the max8513 positive linear-regulator output voltage, v out3p , is set with a resistive-divider from out3p to fb3p to gnd. first, select r14 resistance value (below 1k ? ). then, solve for r13 so: where v out3p can range from +0.8v to +27v. out3n voltage selection (npn) the max8514? negative linear-regulator output volt- age, v out3n , is a negative regulated voltage devel- oped through the pass transistor q4 (max8514 typical applications circuits ). a resistive-divider from out3n to fb3n to v ref3n forces v fb3n to regulate to 0v. calculate v out3n by first selecting r14 the resistor from v ref3n to fb3n to be below 5k ? , where v ref3n is any positive voltage (usually v out1 ). r13 is then cal- culated by: sup3n is the supply input for out3n? transconduc- tance amplifier. when out3n is used, sup3n must be connected to a voltage supply between 1.5v and 5.5v that can source at least 25ma. typically, v out1 can be used as the supply input for sup3n. stability requirements the max8513/max8514s?drv3p and drv3n outputs are designed to drive bipolar transistors (pnp types for the max8513 with the drv3p output, and npn types for the max8514 with the drv3n output). these bipolar transistors form linear regulators with positive outputs (max8513 from 0.8v to 27v) and negative outputs (max8514 from -18v to -1v). an internal transconduc- tance amplifier is used to drive the external pass tran- sistors. the transconductance amplifier, pass transistor? specifications, the base-emitter resistor, and the output capacitor determine the loop stability. the total dc loop gain (a v ) is the product of the gains of the internal transconductance amplifier, the gain from base to collector of the pass transistor (q4 in the typical applications circuits ), and the gain of the feed- back divider. the transconductance amplifier regulates the output voltage by controlling the pass transistor? base cur- rent. its dc gain is approximately: where g c3_ is typically 0.6s (out3p) and 0.36s (out3n), r in is the input resistance of q4, and can be calculated by: the dc gain for the transistor (q4), including the feed- back divider, is approximately: v t is the thermal voltage for the transistor (typically 26mv at t a = +27 c). the total dc loop gain for out3_ is: a dominant pole (f pole1 ) is created from the output capacitance and load resistance: unity-gain crossover (f c_out3_ ) should occur at: a second pole is set by the input capacitance to the base of q4 (c q4in ), any external base-to-emitter capacitance (c be , see the base-drive noise reduction section and figure 7), the transistor? input resistance (r in ), and the base-to-emitter pullup resistor (r12): faf c out v pole __ 31 = f cr i cv pole out out out max out out 1 33 3 33 1 22 = = _ _ ag rr a vc in q = () 34 12 __ || a v vt for out p or a vv vv v qp ref qn out n ref n ref n out n t 4 4 33 33 3 = = () - r mv i in out _ = ? ? ? ? ? ? 26 3 grr cin 3 12 _ || r v v r out n ref n 13 14 3 3 = - rr v v out p 13 14 08 3 . = ? ? ? ? ? ? -1
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset 30 ______________________________________________________________________________________ if the second pole occurs well after unity-gain crossover, the linear regulator remains stable. if not, then increase the output capacitance c out3 (c8 in the typical applications circuits ) so: if high-esr capacitors are used for the output capaci- tor (c out3 ), then cancel the esr zero with a pole at fb3_. this is accomplished by adding a capacitor (c fb3_ ) from fb3_ to gnd so: out3_ output capacitors connect at least a 1? capacitor between the linear regu- lator? output and ground, as close to the max8513/ max8514 and the external pass transistors as possible. depending on the selected pass transistor, larger capaci- tor values may be required for stability (see the stability requirements section). once the minimum capacitor value for stability is determined, verify that the linear regu- lator? output does not contain excessive noise. although adequate for stability, small capacitor values can provide too much bandwidth, making the linear regulator sensitive to noise. larger capacitor values reduce the bandwidth, thereby reducing the regulator? noise sensitivity. for the negative linear regulator, if noise on the ground reference causes the design to be marginally stable, bypass the negative output back to its reference voltage (v ref3n , figure 6). this technique reduces the differential noise on the output. ensure the voltage rating of the capacitor exceeds the output voltage. base-drive noise reduction the high-impedance base driver is susceptible to system noise, especially when the linear regulator is lightly loaded. capacitively coupled switching noise or induc- tively coupled emi on the base drive causes fluctuations in the base current, which appear as noise on the linear regulator? output. to avoid this, keep the base-drive traces away from the step-down converter and as short as possible to minimize noise coupling. resistors in series with the gate drivers (dh and dl) reduce the lx switching noise generated by the step-down converter. additionally, a bypass capacitor (c be ) can be placed across the base-to-emitter resistor (figure 7). this bypass capacitor, in addition to the transistor? input capaci- tance, reduces the frequency of the second pole (f pole2 ) that could destabilize the linear regulator (see the stability requirements section). therefore, the stability require- ments determine the maximum base-to-emitter capaci- tance (c be ) that can be added. transformer selection in systems where the step-down controller? output (out1) is not the highest voltage, a transformer can be used to provide additional post-regulated, high-voltage outputs. the transformer generates unregulated high- voltage supplies that power the positive and negative linear regulators. these unregulated supply voltages must be high enough to keep the pass transistors from saturating. for positive output voltages, connect the transformer as shown in the typical applications circuits where the minimum turns ratio (n 2 /n 1 ) is deter- mined by: where v q4(sat) is out3p? pass transistor? saturation voltage under full load. since power transfer occurs when the low-side mosfet is on (dl = high), the trans- former cannot support heavy loads with high duty cycles on v out1 . minimum load requirements (linear regulators) under no-load conditions, leakage currents from the pass transistors supply the output capacitor, even when the transistor is off. generally, this is not a prob- lem since the feedback resistors?current drains the excess charge. however, charge can build up on the output capacitor over temperature, making v out2/3 rise above its set point. care must be taken to ensure the feedback resistors?current exceeds the pass transis- tor? leakage current over the entire temperature range. thermal consideration the power dissipated by the series pass transistor is calculated by: where v in is the input to the transistor of the ldo and the absolute value of the difference between v in and v out2/3 is taken. v in is derived from the transformer winding ratio. the transistor must be adequately heat sunk to prevent a thermal runaway condition. refer to the transistor data sheet for thermal calculation. pvv i din out out || // = () - 23 23 n n vvv v out q sat d out 2 1 34 2 1 ++ _() c rr f fb esr 3 1 234 _ || = ff pole c out 23 2 __ > f cc rr pole be q in in 2 4 1 212 = + () ||
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset ______________________________________________________________________________________ 31 pvl in gnd comp1 bst dh lx dl freq pgnd drv2 fb2 drv3p fb3p l1a c1 1 f d1 100ma, 30v (cmosh-3) c2 10 f c5 4.7nf r3 6.8k ? c3 0.1 f q1 q2 q3 30v, 23a n-channel mosfet (irlr2703) r5 340 ? r6 160 ? r7 10.7k ? c6 10 f v out2 2.5v, 1.5a v out1 3.3v, 2a v in fb1 por 30v, 5.5a dual n-channel (fds6984s) ref pfo seq pfi c9 0.1 f r10 68.1k ? r11 12.4k ? r8 100k ? r9 100k ? vl en/sync sup2 c10 2.2 f r15 10 ? c12 33pf fb1 r a 100 ? c a 0.68 f ss csp csn ilim v out1 csp r17 665k ? r18 66.5k ? c13 0.1 f coupled inductor l1a = 1.8 h, 4.5a/0.01 ? n2/n1 = 20:6 (coiltronics, ctx 03-16101) r13 11.3k ? r12 1k ? v out3p 12v, 50ma r14 806 ? l1b c8 1 f c7 1 f q4 40v, 200ma pnp (mmbt3906) d2 cmpd4448 c4 47 f r1 13.3k ? r2 8.06k ? c11 680pf r4 620 ? csn r19 200 ? r20 200 ? c14 0.47 f c20 1000pf r25 5.1 ? csn csp c22 1000pf pfo por ic1 max8513 r26 1.5k ? figure 5. max8513 typical applications circuit
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset 32 ______________________________________________________________________________________ pvl in gnd comp1 bst dh lx dl freq pgnd drv2 fb2 l1a c1 1 f d1 100ma, 30v (cmosh-3) c2 10 f c5 4.7nf r3 6.8k ? c3 0.1 f q1 q2 q3 30v, 23a n-channel mosfet (irlr2703) r5 1.74k ? r6 806 ? r7 10.7k ? c6 10 f v out2 2.5v, 1.5a v out1 3.3v, 2a v in 9v to 16v fb1 por 30v, 5.5a dual n-channel (fds6984s) ref pfo seq pfi c9 0.1 f r10 68.1k ? r11 12.4k ? r8 100k ? r9 100k ? vl en/sync sup2 c10 2.2 f r15 10 ? c12 33pf fb1 r a 100 ? c a 0.68 f ss csp csn ilim v out1 csp r17 665k ? r18 66.5k ? c13 0.1 f coupled inductor l1a = 1.8 h, 4.5a/0.01 ? sup3n c4 47 f r1 13.3k ? r2 8.06k ? c11 680pf r4 620 ? csn r19 200 ? r20 200 ? c14 0.47 f c20 1000pf r25 5.1 ? csn csp c22 1000pf r14 3.31k ? v ref3n ic1 max8514 drv3p fb3p r13 12.1k ? r12 1k ? v out3p 12v, 50ma l1b c8 1 f c7 1 f q4 40v, 200ma npn (mmbt3904) d2 cmpd4448 r26 1.5k ? pfo por figure 6. max8514 typical applications circuit
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset ______________________________________________________________________________________ 33 applications information pc board layout guidelines careful pc board layout is critical to achieve low switching losses and clean, stable operation. the switching power stage requires particular attention. follow these guidelines for good pc board layout: place decoupling capacitors as close to the ic pins as possible. keep separate the power-ground plane (con- nect to the sources of the low-side mosfet, pgnd, and the output capacitor? return). connect the input decoupling capacitors across the drain of the high-side mosfets and the source of the low-side mosfets. the signal-ground plane (connected to gnd) is con- nected to the rest of the circuit-ground return. the two ground planes then connect together with a single con- nection at the ic. keep the high-current paths as short as possible. connect the drains of the mosfets to a large copper area to help in cooling the devices, further improving efficiency and long-term reliability. 1) ensure all feedback connections are short and direct. place the feedback resistors as close to the ic as possible. 2) route high-speed switching nodes away from sen- sitive analog areas (fb_, comp, ilim). 3) ensure the current-sense paths for csp and csn run parallel and close together to cancel any noise pickup. 4) a reference pc board layout included in the max8513 evaluation kit is also provided to further aid layout. b) negative output voltage v out1 v out1 v out1 c7 v out3n q4 c8 r12 cbe r13 r14 drv3p a) positive output voltage fb3p v out3p c7 q4 c8 r12 c be r14 r13 fb3n drv3n sup3n l1b l1b max8513 max8514 figure 7. base-drive noise reduction
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset 34 ______________________________________________________________________________________ chip information transistor count: 4824 process: bicmos pin configurations 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ss csn csp ilim fb3p por fb2 in drv3p n.c. sync/en seq sup2 drv2 gnd ref freq fb1 comp1 vl pgnd pvl dl bst lx dh pfo pfi 28 qsop top view max8513 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ss csn csp ilim fb3n por fb2 in drv3n sup3n sync/en seq sup2 drv2 gnd ref freq fb1 comp1 vl pgnd pvl dl bst lx dh pfo pfi 28 qsop max8514
max8513/max8514 wide-input, high-frequency, triple-output supplies with voltage monitor and power-on reset maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 35 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) qsop.eps e 1 1 21-0055 package outline, qsop .150", .025" lead pitch

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